PCB technology / Layered interconnect

Multilayer PCB Manufacturing (4–40 Layers)

Multilayer PCB manufacturing combines routing density, reference planes and power distribution in a controlled stackup. A 2 layer, 4 layer or 6 layer PCB stackup is selected from the routing, signal and power requirements rather than treated as a duplicate door page.

4–40 layersStandard range
±10%Standard impedance
15:1Standard aspect ratio
0.10 mmLaser via
Engineering choices

Layer count follows routing and reference needs.

Board size alone does not set the layer count. Plane count, escape routing, signal integrity and lamination cycles are the decisions that matter.

Volume sweet spot

4–6 layers

A routing pair plus dedicated power and ground planes for mainstream products.

High-speed routing

8–12 layers

Multiple reference planes for DDR, PCIe and mixed-signal architectures.

Dense systems

12–18 layers

Backplanes, line cards and complex analog/digital partitioning.

Advanced stackups

18–40 layers

High-count backplanes and instrumentation requiring careful lamination planning.

Technical reference

Two process windows, one stackup decision

Standard production covers most multilayer designs. High-count, HDI or unusually tight geometries move into an advanced review path.

Multilayer PCB product sample
Copper balance, lamination sequence and reference-plane continuity determine whether a multilayer design scales cleanly.Final capability is confirmed from the complete production package.

Standard multilayer specifications

The baseline volume production window

Layer count1–40 layers
Base materialsFR-4, High-Tg FR-4, halogen-free FR-4, Rogers, Taconic/AGC, PI, aluminum, PTFE/Teflon, F4B and other specialty laminates
Board thickness0.10–10.0 mm
Minimum trace / spacing2.5 / 2.5 mil (0.0625 / 0.0625 mm)
Minimum mechanical drill0.15 mm
Minimum laser via0.10 mm
Standard aspect ratioUp to 15:1
Copper thickness0.5–12 oz, depending on board type and construction
Controlled impedance±10% standard; ±5% for tighter requirements
Warpage≤0.75% standard; ≤0.5% available when specified
Surface finishesHASL, Lead-Free HASL, OSP, ENIG, Immersion Silver, Immersion Tin, ENEPIG, Hard Gold, Gold Finger and selective finishes

Advanced multilayer and HDI

R&D prototyping and high-end builds

Layer countUp to 64 layers for prototype / engineering builds
Minimum trace / spacing2 / 2 mil (0.05 / 0.05 mm)
Standard mechanical drill0.15 mm
Advanced / special hole capabilityDown to 0.10 mm, subject to design and process review
Minimum laser microvia0.075 mm
Aspect ratioUp to 20:1 for qualified designs; 15:1 or below for standard advanced production
HDI structures1+N+1, 2+N+2, multi-step HDI and Any-Layer HDI
Via technologyBlind vias, buried vias, stacked vias, staggered vias, via-in-pad, VIPPO / POFV, resin-filled and plated-over vias
Sequential laminationSupported
Any-layer interconnectionSupported
Back drillingSupported
Controlled impedance±10% standard; ±5% for tighter requirements
Warpage control≤0.5% available when specified, subject to stack-up and design review
High-speed / high-frequency materialsRogers, Taconic/AGC, PTFE/Teflon, F4B, High-Tg FR-4 and other low-loss specialty laminates

Capability values are design-dependent. Material, copper weight, layer count, via structure, finished thickness and surface finish can change the achievable combination.

Design context

Via structure is a major cost driver.

Every sequential lamination cycle adds process steps. The engineering goal is to preserve routing density while removing avoidable via complexity.

  • Plated through-holes connect all layers at the lowest process cost
  • Blind and buried vias free routing channels but add lamination work
  • Back drilling removes unused stubs on high-speed interconnects
  • Via-in-pad and laser microvias support fine-pitch BGA escape routing
Through-hole viasBlind viasBuried viasLaser microviasVia-in-padBack drillingStacked viasStaggered vias
Multilayer PCB product sample with dense routing and component lands
Engineering review

Confirm the multilayer stackup and via structure before release.

Review layer symmetry, copper balance, via architecture, impedance references and lamination cycles as one multilayer build system.

Explore DFM review
Stackup symmetry and copper balance
Target impedance against laminate Dk and finished thickness
Aspect ratio and annular-ring verification
Blind and buried via lamination-cycle count
Reference-plane continuity across high-speed routes
Layer-count reduction where the routing allows it
Practical fit

Where multilayer construction earns its place

Use these examples as a starting point. The board construction still follows the product’s electrical, mechanical and qualification requirements.

Frequently asked questions

Multilayer PCB manufacturing FAQ

These answers cover the stackup, via and impedance questions that commonly affect multilayer PCB release.

What is the maximum standard multilayer count?

The standard volume production range is 4–40 layers. Prototype and engineering stackups can support up to 64 layers and require a separate engineering evaluation.

Do you support blind and buried vias?

Yes. Blind, buried, stacked and staggered microvia structures are available. The lamination sequence is reviewed because it drives both reliability and cost.

Can PCBArise propose the stackup?

Yes. Send the netlist, target impedance and material constraints. Engineering can propose the lowest practical layer count and a manufacturable stackup.

What impedance tolerance is available?

Standard multilayer production targets ±10%. ±5% is available for tighter requirements after the full stackup and material system are confirmed.

Have a board in mind? Let’s define the right build path.

Share the available Gerber, ODB++, drawing, stackup or project requirements with the PCBArise team.